1. Field of the Invention
This invention relates to a video signal apparatus with noise reduction and edge enhancement for processing a video signal.
2. Description of the Prior Art
A video signal processing apparatus for processing a video signal with reduction of noise and edge enhancement is known. FIG. 3 is a block diagram of a prior art video signal processing apparatus. This prior art video processing apparatus comprises a line memory 2 for delaying a video signal inputted to an input terminal Ti' by one horizontal line (scanning) period (1H), a line memory 3 for delaying an output of the line memory 2 by 1H, a noise reduction circuit 1, supplied with the video signal, the output of the line memory 2, and an output of the line memory 3, for reducing noises in the video signal through two-dimensional filtering, a line memory 8 for delaying an output of the noise reduction circuit 1 by 1H, a line memory 9 for delaying an output of the line memory 8 by 1H, a horizontal edge enhancement signal generation circuit 5 for generating a horizontal edge enhancement signal from an output of the line memory 8, a vertical edge enhancement signal generation circuit 4 for generating a vertical edge enhancement signal from outputs of the noise reduction circuit 1, the line memory 8, and the line memory 9, an adder 6 for summing the horizontal edge enhancement signal and the vertical edge enhancement signal, and an adder 7 for summing the output of the line memory 9 and an output of the adder 6.
The noise reduction circuit 1 reducing noise in the video signal through two-dimensional filtering is disclosed in Japanese patent application provisional publication No. 6-86104.
An operation of this prior art video processing apparatus will be described. FIG. 4 is a graphical drawing of the prior art video signal processing apparatus showing waveforms of output signals at respective points shown in FIG. 3. The line memory 2 delays the video signal, having a waveform 201, inputted through the input terminal Ti', by one horizontal scanning period (1H) to produce a one-H delayed video signal. The line memory 3 delays the output of the line memory 2 to produce two-H delayed video signal. The noise reduction circuit 1, supplied with the video signal, the one-H delayed video signal, and the two-H delayed video signal reduces noises in the video signal through two-dimensional filtering as shown by a waveform 202. The line memory 8 delays the output of the noise reduction circuit 1 by 1H. The line memory 9 delays the output of the line memory 8 by one horizontal scanning line. The horizontal edge enhancement signal generation circuit 5 generates the horizontal edge enhancement signal from the output of the line memory 8. The vertical edge enhancement signal generation circuit 4 generates the vertical edge enhancement signal from outputs of the noise reduction circuit 1, the line memory 8, the line memory 9. The adder 6 sums the horizontal edge enhancement signal and the vertical edge enhancement signal to produce an edge enhancement signal as shown by a waveform 203. The adder 7 sums the output of the line memory 9 and an output of the adder 6 to produce an edge enhanced video signal as shown by a waveform 204.